Overview of On-Chip Performance Monitors for Clock Signals

For a safety-critical IC, on-chip monitors have become more and more necessary to discover run-time performance hazards as soon as possible. The general performance metrics that have been targeted in the literature are numerous, such as, the maximum operating speed of a circuit component, the interconnect delay, the transition time or leaking current at an IO pin, etc. In this short paper, we will briefly summarize the features of some of them related to a clock signal, in particular, the performance monitors for excessive jitters, phase errors, or duty-cycle errors. Even with only mature process technology, e.g., a 90nm CMOS process, fine-resolution monitors with the time resolution of only a few picoseconds can still be easily achieved by cell-based designs.