A low jitter 50Gb/s PAM4 CDR of Receiver in 40nm CMOS Technology

This paper presents a low jitter 50 Gb/s clock and data recovery (CDR) circuit of receiver for 4-level pulse-amplitude modulation (PAM4) signal. This PAM4 CDR mainly includes a comparator which works as a 3-level slicer to convert the PAM4 signal into three path NRZ temperature codes signal, a decoder that converts the thermometer code signal into NRZ signal output, and a half-rate CDR which recovers the clock signal from the input data. Simulation results show that the peak-to-peak jitter of the recovered clock and data are 1.6ps and 3ps, respectively. In 40nm CMOS technology, the power consumption of the whole PAM4 CDR is about 450mW with supply voltage of 1.2V.