An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing

This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.