Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks

With the rise of IoT and its many applications, the capabilities of sensor nodes in wireless sensor networks have increased due to the large amounts of sensed data that incur a significant amount of workload at the network core. As such, edge computing applications, which take computing away from the network core into the network edge, become more widely used. This paper presents a pipelined RISC-V RV32IMC processor with interrupt support as a solution to this challenge. For communication with peripherals, the processor supports the protocols I
²
C, SPI, and UART. Design optimizations, delay balancing and clock gating, resulted in a 13.3% maximum operating frequency increase and a 23.3% reduction in the dynamic power consumption of the core processor. The implemented processor utilizes an average core power of 30.752 mW while operating at a frequency of 50 MHz on a Digilent Arty A7 Board with a Xilinx Artix-7 FPGA.