System Implementation of Synchronized SS-CDMA for QZSS Safely Confirmation System

In this paper, we construct and evaluate central processing unit - intellectual property (CPU-IP) core as one of the considerations of system on chip (SoC) implementation of the transmission timing control system, in synchronized Spread-Spectrum Code-Division Multiple-Access (SS-CDMA) communication for the location and short message communication system using Quasi-Zenith Satellite System (QZSS). As a result of evaluating the transmission timing calculation unit with the CPU - IP core constructed on the field programmable gate array (FPGA), it is possible to construct a system with the same performance as that constructed with the conventional micro controller unit (MCU). In addition, we experiment with the transmission timing control by connecting the construct transmission timing calculation unit and the conventional delay control unit. As a result, the system is found to be operating normally. Since the delay control unit is a conventional one, but, this result is sufficient to result as a foothold for SoC implement of the transmission timing control system.