FDSOI Sige Morphology Optimization on Boundary of AA and STI

As short channel effect turns into a major constraint for traditional bulk silicon devices when CMOS technology scales down to 22nm and beyond, fully depleted silicon on insulator (FDSOI) devices becomes more popular in integrated circuit manufacture. The selective SiGe epitaxial is applied for FDSOI PMOSFET as raised source and drain to enhance hole mobility, whereas a defect, SiGe shrinkage, that SiGe non-growth on boundary of STI and AA can kill device yield. In this paper, an optimized Siconi pre-clean process and a novel Si-nucleation layer are proposed to improve the SiGe shrinkage, thereby boosting the device performance.