A New Integration flow Study of ONO film Uniformity and Silicon recess improvement for 2T-SONOS Flash

Non-volatile SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash shows better application as the advantages of low program voltage, long-term data retention, good compatibility of CMOS strategy and low cost on memory device. But the device and process window also narrowed especially for cell size continue shrink. This paper applies a new integration flow study of ONO film uniformity and silicon recess improvement for 2T-SONOS Flash on 40nm Tech. Traditional non-SONOS ONO film remove method of LP device is by dry etch, but on 40nm scale, the process window is not enough due to pad oxide thinner with cell size shrink. With much study, we apply a new method that non-SONOS ONO film remove by wet, at the same time, in consideration of select gate silicon recess, we optimize Wet etch process 2 in 1. On one hand, it can enlarge ONO etch process window, optimize ONO uniformity and match production needs, on the other hand, it can improve select gate silicon recess to further reduce the risk of NiSi piping and improve yield, Furthermore, the cost can drop remarkably when use 2 in 1 Wet process particularly on FAB.