Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-all-around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.