A Method of Verification in Chisel Based Deep Learning Accelerator Design

Chisel is a new generation of hardware construction language (HCL) for agile development. More and more developers have developed their project in agile design. At the same time, a considerable part of Verilog-based design has also been released in agile design versions. However, there is no comprehensive verification flow for Chisel based design. Due to the difficulties of verification in Chisel based design, it is a tough task to attach Chisel based design on Verilog based design. We purpose a feasible verification flow in chisel-based deep learning accelerator (DLA) design, which is composed by performance equivalence check at module-level and function equivalence check at pin-level. Compared to Universe Verification Method in RTL level codes that cost considerable time and funds, this verification flow improves the verification efficiency and reduce the difficulty of debug.