Software-Behavior-Aware Prefetching Method in Embedded RISC Systems

An efficient instruction-based software behavior model is proposed to fully utilize the benefits of high-performance cache. This new model, which is established using process algebra, is hardware-aware (e.g., instruction set). To examine the benefits of our proposed software behavior model, an embedded RISC system is chosen in a case study, where our proposed software behavior model achieves an accuracy of more than 96% and helps to improve the cache hit rate by over 5%.