A Systematic Approach to Localize NVM Inter-Poly Defects using Nanoprobing Techniques

The continuous growth and advancements of semiconductor devices for automotive applications and internet-of-things drive the demand and scaling of embedded non-volatile memories (eNVM). Existing eNVM landscape in 40nm and 28nm advanced processes is dominated by split-gate flash memory devices [1] where inter-poly oxide (IPO) defect is one of the most challenging types of defect to localize [2]. This is due to the global polysilicon lines that are used as shared wordlines/select gate, control gate or erase gate. They could be shared among thousands of NVM cells and inter-poly defects would typically surface as entire row failure. Even if enhanced NVM testing could reveal the suspected failing bit, the IPO defect site may be marginally shifted off the failing bit. Thus, direct cross-section Transmittance Electron Microscopy (TEM) approach, with limited view area, might not be effective. In this paper, a case study on a split-gate automotive grade eNVM suffering from read/write cycling failure was described. In this case study, a systematic approach using nanoprobe to first characterize the inter-poly leakage to identify the failing column, followed by Electron Beam Absorbed Current (EBAC) analysis within the failing column, was adopted to effectively localize inter-poly defect and validate NVM bitmap accuracy.