Design and Performance Analysis of FD Silicon on Insulator MOSFET

In this work, Fully Depleted-Silicon on Insulator (FD-SOI) MOSFET is designed, and the impact of silicon thickness, source doping, and metal gate work function variations are investigated to analyze the various device performance parameters. Simulated results of ON current, OFF current, energy band diagram, gate capacitance, and drain capacitance are analyzed. In addition to this, drain induced barrier lowering (DIBL), the threshold voltage (V
_th
), sub-threshold slope (SS) variations are also evaluated. The results depict that the threshold voltage increases with the increment in Si surface thickness and source doping and it is 0.25V for 10 nm Si surface layer. The DIBL is 0.02 (V/V), and SS of 66.13 (mV/dec) is evaluated for the same Si surface layer thickness. Silvaco Atlas-2D TCAD simulator is used to estimate the various results.