A Design Flow for Synthesis of Quasi Delay Insensitive Combinational Circuits

Nowadays, synchronous digital circuits design in MOS technology can cause difficulties, this is due to the clock signal. The asynchronous paradigm presents interesting features focused on to solve the clock signal problem. An important class of the asynchronous paradigm is the known Quasi Delay Insensitive (QDI) circuits that can also be used for critical applications, because they are robust to temperature variations, to wire and gate delays, and to supply voltage variation, having low electromagnetic emissions and low noise. QDI combinational circuits are designed as a block of functions whose indicability shows the robustness of the circuit communication with the environment. This paper presents an architecture based on basic gates that do not use C-elements to implement QDI functions. In addition, an approach to the synthesis of QDI function blocks and a disjoint logic minimization method (DSOP) for simple output. The new architecture as the DSOP method has been tested for a set of benchmarks. We can highlight the area reduction of up to 64.3% compared to literature QDI architectures.