Study of Ambipolar Current of a Steep Slope Tunneling FET with Drain Underlap

The tunneling field effect transistor is basically a gated p-i-n diode, is recently under rising interest due to its potential to deliver steep on-off slopes and its ability in operating at supply voltages below 0.5 V. We present simulation results of double gate pocket doped silicon n-channel Tunnel FET on the investigation of the influences of drain underlap. Ambipolar current behavior in details with gate-drain underlap is studied and it is observed that ambipolar current could be completely suppressed if 8-nm gate-drain underlap is used.