Integration of ALD high-k dipole layers into CMOS SOI nanowire FETs for bi-directional threshold voltage engineering

In this report, we successfully demonstrate V
T
(threshold voltage) tuning in both n- and p- SOI nanowire FETs (NWFET) using ultrathin atomic layer deposition (ALD) dipole layers (Y
2
O
3
and Al
2
O
3
) inserted directly under the ALD HfO
2
(3 nm). 0.7 nm of Y
2
O
3
inserted between bottom SiO
x
(< 1 nm) and top HfO
2
(3 nm) shifted the V
T
by -138 mV and -58 mV for n- and p-NWFET, respectively while 0.7 nm Al
2
O
3
shifted the V
T
of n-NWFET by +219 mV and +134 mV for p-NWFET. V
T
shift on planar SOI FETs were also observed with the similar trend only when such ALD dipole layers were inserted in direct contact with SiO
x
. MOS capacitor’s V
FB
(flat band voltage) showed similar tunability with ALD dipole layer positioned near the SiO
x
/Si channel interface. Intermixing multiple dipole layers can more precisely tune the V
T
in desired direction and strengths by partially neutralizing each other.