Comparative Study on the Energy Profile of NBTI-Related Defects in Si and Ferroelectric p-FinFETs

A comparative study is carried out to understand the defects in p-type ferroelectric FinFETs (FE-FinFETs) under negative bias temperature condition. Two types of traps, preexisting and generated ones, are unambiguously identified and their energy profiles are separated. Comparing with their Si-based counterpart, it is found that both devices exhibit similar pre-existing traps, however, generated traps in FE-FinFET show much weaker stress bias and temperature dependence due to suppressed bulk trap generation. The results suggest that the pre-existing traps are physically located within the SiO
₂
interfacial layer (IL) while the bulk trap generation is mainly located in the high-k layer. The suppressed bulk trap generation process could be ascribed to Zirconium in the high-k dielectric, which might strengthen oxide bonds and suppress the generation of precursors of generated bulk traps.