A Vertical Combo Spacer to Optimize Electrothermal Characteristics of 7-nm Nanosheet Gate-All-Around Transistor

In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA) transistor with a vertical combo spacer and different underlap/overlap channels is studied by the 3-D TCAD simulation. To achieve high authoritative evidences, the I
_d
-V
_g
characteristic with SHE is calibrated with the experimental data. First, the change of electrical characteristic introduced by different dielectrics of a single-k spacer is investigated, and the results show that the current of ON-state (I
_ON
) is a power function of relative permittivity, whereas the OFF-state (I
_OFF
) exhibits a linear dependence. Second, a novel vertically wrapped combo spacer is proposed to achieve a compromise between thermal characteristic and electrical performance for the first time. The electrothermal characteristics of the combo spacer under different underlap/overlap channels are also studied, and the results showed that the combo spacer composed of inner Si
₃
N
₄
and outer HfO
₂
has the highest ION/IOFF but smaller thermal resistance and lower lattice temperature compared with other different combinations. At last, a CMOS inverter with Si
₃
N
₄
/HfO
₂
combo spacer is demonstrated for its improvement in propagation delay.