Detection and Classification of Typical Defects in TSV and RDL

Three-dimensional integrated circuit (3D IC) is one of the most promising solution to keep improving performance, saving area and power. As a key part of 3D integration, through silicon vias (TSV) assembling, manufacturing and usage process may introduce various kinds of defects. This paper proposed a nondestructive defect detection and classification scheme based on a k-nearest neighbors (KNN) algorithm. Two on-chip measurable quantities, signal delay and frequency, are adopted as feature vectors for our algorithm, which make it compatible with both post-bonding test and on-chip self-test. The simulation results show the signal delay of TSVs with voids inside remains the same or even better than the defect-free cases. However, for those interconnects with voids or cracks at the TSV-RDL joints, delays are obvious. Especially for the cases with defects at both end of a TSV, the performance degradation should be taken into account. Our results show that the well-trained machine learning algorithm can classify the defect type in a reliable way, and may play an important role in signal integrity analysis and build-in self-repair (BISR) circuit design.