A Distinctive Approach for Vedic-Based Squaring Circuit

A novel method for squaring binary numbers using Vedic mathematics is proposed in this paper. The implementation of the binary squaring circuit uses the improved Vedic multiplier architecture. The circuit is designed in VHDL using the ModeSim tool from Mentor Graphics. The circuit synthesis is performed using the Xilinx ISE 14.1. The HDL-based simulation is presented for 4-bit and 8-bit. The design can easily be expanded for large bit sized inputs. The device utilization and delay comparison are presented using different families of FPGA. The binary squaring circuit presented in this paper show better speed performance than the previously reported squaring circuits.