An FPGA based implementation of the Conjugate Gradient Kernels

The Conjugate Gradient (CG) is frequently used iterative methods to solve Systems of Linear Equations (SLEs). The CG has a faster convergence rate and higher accuracy. It is widely used for many scientific applications such as meteorology, groundwater flow problems, studying satellite data, ocean circulation modeling, molecular dynamics simulations, real-time power quality assessment, and a neural robot controller, etc. It can be implemented on CPUs, GPUs and in Field Programmable Gate Arrays (FPGAs). FPGAs have been shown to provide an order of magnitude to speed up for various computation-intensive applications. However, a Hardware Description Language (HDL) based FPGA implementation for all the arithmetic modules requires considerable development time and the designer needs to be knowledgeable in hardware design as well as in HDL programming. Using IP cores can reduce the development time and design complexity. Prominently, CG has basic three computational kernels and amongst them, Matrix-Vector Multiplication (MVM) is the most computationally intensive kernel. Optimizing MVM kernels with higher throughput can reduce the computation time required for each iteration of CG. In this research, three basic kernels of CG are implemented on FPGAs using floating-point IP cores. The results show that with an FPGA-based implementation of CG we achieved a significant order-of-magnitude over the software implementation (Intel Xenon ® CPU E5-2650 V2, 2.60 GHz) of the CG using Arria 10 1150 GX.