Pipelined Fast Fourier Transform (FFT) Processor Power Optimization

This paper presents the pipelined Fast Fourier Transform (FFT) processor power optimization. Pipelined FFT processor comprises of several sub-modules such as data buffer, shifter, and rotator (butterfly) which introduced power consumption to the circuit when in a hierarchical design. The objectives of this paper are, first, to study the power consumption in term of total dynamic power and cell leakage power during the hierarchical condition for different type of pipelined FFT and next, the objective is to study the power saving after the optimization process, where the design is flattened without sub-modules. This paper focuses on 16-point and 64-point pipelined FFT with radix-4 and radix-8 algorithms. The design process is in Verilog coding and simulation is in Modelsim Altera. Total dynamic power and cell leakage power for before and after the optimization process is performed using Synopsis. Overall, 16-point pipelined FFT with radix-4 algorithm has the best total dynamic power saving at 31.33% and 64-point pipelined FFT with radix-8 has the best cell leakage power saving with 58.83%. However, all pipelined FFT show lower power consumption after the optimization process. In conclusion, after the flattening process, power consumption reduced significantly.