VLSI Architecture for Fine Grained Pipelined Feature Extraction using Histogram of Oriented Gradient

The most popular field to support the massive growth of the intelligent based system in the recent year is object detection. The fundamental of the object detection technology is feature extraction. It becomes the main challenge due to the variability of application and the computation requirement. One of the challenging issue is to implement this computing system into hardware level architecture to get lower power, high speed, and lower cost computing system. According to some study, Histogram of Oriented Gradient (HOG) is the current most robust feature extraction. This paper proposes a novel hardware architecture for HOG based feature extraction. The architecture brings performance improvement and it opens various benefit in the utilization of VLSI system instead of GPU. This architecture implements tasks for HOG feature extraction including gradient extractor using edge filter algorithms, polar data representation using vectoring mode CORDIC, and histogram normalization using Barni's approximation method. The simulation shows very low (fraction of frame rate) output latency for various image size, therefore the system could support real-time processing, for those imaging rate. The processor successfully implemented for Stratix IV FPGA EP4SGX230 with logic utilization about 10%. With 100 MHz clock rate, it potentially performs up to 1.5 times faster than the GPU fast HOG implementation.