An approximate DRAM with efficient refresh schemes for low power deep learning applications

To avoid the accuracy drop caused by slowing down the refresh rate of a DRAM, the proposed approximate DRAM flexibly controls the refresh operation for different bits of data. Data are reorganized and mapped to different DRAM devices according to their bit significance. More critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. Compared to the conventional DRAM, the proposed approximate DRAM requires only a separation of the chip select signal for each device in a DRAM rank and a minor change in the memory controller. Simulation results show that the refresh power consumption is reduced by 66.5 % with a negligible accuracy drop in computation for state-of-the-art deep networks.