A novel bit-line process using poly-Si masked dual-damascene (PMDD) for 0.13 /spl mu/m DRAMs and beyond

A novel middle-of-line (MOL) DRAM cell technology based on the poly-Si masked dual-damascene tungsten bit-line (BL) has been developed. New technologies such as borderless rectangular metal contacts, a thermally robust tri-layer barrier metal, well-controlled dry/wet recessed damascene BLs, and a low-temperature LPCVD-Si/sub 3/N/sub 4/ cap for a storage node self-aligned contact make it possible to realize the successful MOL integration for 0.13 /spl mu/m DRAMs. Since this process offers a sufficient alignment margin and a significant reduction of chip size as well as a reduced thermal budget, it is expected to be useful for making the future gigabit DRAMs and logic embedded DRAMs.