Ultra High Density Package Design and Electrical Analysis in High Performance Computing Application

With regard to the development of the Internet of Things, artificial intelligence, autonomous driving and the robotic development applications, the high bandwidth and low latency performance are needed. In this trend, the high performance semiconductor integrated package have become an important product, such as FOCoS(Fan-out Chip on Substrate) and 2.5D Interposer which applied in high performance computing (HPC). The first application used in this kind ultra-high density package is high performance computing (HPC) like GPU, there is an ASIC die and multi-HBM dies on fan-out or silicon interposer structure. Between ASIC die and HBM die, there are lots of high speed signal lines, and lots of metal grid, vias for power/ground domain. A real product with an ASIC die and 2 HBM dies is designed in Chip Last FOCoS and 2.5D interpsoer structures, the FOCoS and 2.5D interposer design is utilized SiP-id (System in Package intelligent design) design platform to accelerate the ultra-high density I/O routings design cycle time. In electrical performance, the signal integrity and power integrity are compared between FOCoS and 2.5D interposer. The signal eye-diagram of HBM2 and 28Gbps SerDes I/Os are showed in this paper, and the PDN power impedance is also analyzed. This paper is also studied how to optimize the copper coverage rate and DC resistance for core power/ground domain. Both FOCoS and 2.5D interposer ultra high density package structures have a good opportunity in high performance computing application.