Weighted Pseudorandom Based Deterministic Bist for Fault Testing and Self-Healing

The mechanism which involves evaluating design performance is known as Testing. The power dissipation for the circuit in evaluating process is more when compare to standard operation of the circuit. For constricting the power dissipation in testing form delay fault testing method is used in the proposed design. In the proposed design scan architecture with self-healing technique is introduced to enhance the fault coverage. It will be going to sort out number of scan flip flops into uniform group. This paper adds self-healing procedure of scan design that is functioned among two phase clocks for vital scan cell test procedure and faulty scan cell test procedure to pseudorandom pattern generation and deterministic BIST application to increase the fault coverage.