High Density IO Fan-out Design Optimization with Signal Integrity

With the development of the Internet and the rise of artificial intelligence industry, high - performance semiconductor integrated circuits have become a popular product in the semiconductor industry. The 2.5D IC package with ultra-high density I/O is the first structure to be used in high performance computing (HPC) such as GPUs. The silicon interposer applied to GPU or HPC has an ASIC chip and multiple HBM chips. However, the productivity of silicon interposer is always a problem for the realization of ultra - high density I/O products. For considering productivity and performance, TSV-less structure such as FOCoS (fan-out chip on the substrate) was proposed by a few years ago [1]-[5]. There are different processes and applications for Chip First FOCoS and Chip Last FOCoS. In this paper, a real situation with ASIC chip and 2 HBM chips is designed using the 2.5D IC and Chip Last FOCoS structure. In this reality, the interposer and the Fan-Out RDL design are used to accelerate ultra-high density I/O routing by using the SiP-id design platform. Electrical performance including signal integrity (SI) and power integrity (PI) was compared between 2.5D ICs and Chip Last FOCoS. From simulation results, this paper shows transient power supply noise between the two structures and shows the electrical properties of HBM2 and 28Gbps SerDes I/O.