Low Area Overhead Custom Buffering for FFT

In this paper we propose a technique to minimise the area overhead of a double buffered implementation of Radix-4 Fast Fourier Transformation (FFT). Our proposal circumvents the need for double buffering by exploiting opportunities in the specific data reordering of the buffers that are needed when implementing a fully pipelined FFT. By using the same read and write pattern, a single buffer is sufficient to perform data reordering while maintaining data integrity without degrading performance. We demonstrate this approach in an FPGA implementation. As a result of our optimisation, the memory depth can be reduced by a factor of two with very small overhead in control logic complexity.