Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology

Design-technology co-optimization of Intel's first FinFET Anti-Fuse (AF) memory using 22FFL technology is reported. The nMOS based 1T1C bit cell containing TG and TnG is sized to satisfy electrical performance, process marginality, area, and reliability spec. With gate dielectric breakdown as the mechanism of bit storage, it is found that improved gate oxide integrity is beneficial to post-breakdown resistance and overall array yield. Special attention on well design, source/drain optimization, gate height targeting and array layout in the face of 3-dimentional resistor networks in FinFET can significantly modulate array health. A 2.8 k-bit AF array with baseline yield exceeding 99.9% at no added process cost with medium SA margin setting is demonstrated.