A Dynamic Current Mode D-Flipflop for High Speed Application

With the continuous growth of semiconductor technologies, the design of high-speed circuits is a need of the hour. Current Mode Logic (CML), a derivation from Emitter Coupled Logic (ECL) is such an approach with concerns present to be improvised. Targeting that, we have come up with a new design of dynamic CML to structure a power efficient D-Flipflop. The simulations are carried out for 90nm CMOS using Synopsys H-Spice platform at a supply voltage and operating frequency of 1.2V and 10GHz respectively. The device footprint reads an area requirement of 108.624 μm
²
(16.045μm × 6.77μm). This design is noted to dissipate a very low power of 219.05uW and delay of as small as 31.30ps when driven with aperiodic data of 2.5GHz.