A 10-bit 320MS/s Time-Interleaved SAR ADC with an Improved Binary-Scaled Recombination Weighting Capacitor Array

This paper presents a 10-bit 320MS/s time-interleaved successive approximation register (SAR) ADC designed for WLAN (Wireless Local Area Network) applications. An improved binary-scaled recombination weighting capacitor array is disclosed in this work. The proposed SAR ADC achieves a SNDR of 59.9dB and an ENOB of 9.66 with Nyquist frequency at 1.2V and 320MS/s. The power dissipation is 2.2mW and the ADC core only occupies an area of 0.031mm
²
in 40nm CMOS process.