High-speed and high-density chip-to-chip interconnections: trends and techniques

Modern CMOS processes are reaching and breaking the 0.1 /spl mu/m gate length barrier, allowing many tens of millions of digital gates to operate at GHz clock frequencies. This allows the processing of an enormous amount of data every second. It is a major challenge to feed that data volume on and off the chip. Advanced Internet and symmetric multiprocessor (SMP) switch systems are already approaching the 1 Tbit/s aggregate data bandwidth requirement, with a clear trend towards single-chip implementation. This dictates that the input-output (I/O) circuits pump at a rate of 1 Tbit per second into one square inch of silicon and allow the processed Tbit to leave that same chip every second. However, the number of I/O circuits that may be used to address that issue is very limited because of the limited numbers of signal pins that a reasonable package provides. Even with 500 signal I/O pairs of a 2000 pin package, each pair has to transport 4 Gbit/s of user data over a typical backplane distance of 1 m, crossing two dense connectors. This presentation gives an overview of the trends and techniques to address the 1 Tbit/s I/O problem. Four main topics and their implications on packages are addressed: data encoding and modulation, clock and data recovery channel modeling, and channel equalization.