Chip Package Interaction with Cu Pillar Interconnects - Impact of Die Warpage

This paper summarizes the work which was done to understand the die warpage at different temperatures and the influence on the assembly yield in a FCCSP package in combination with Cu pillar first level interconnects. A Cu BEoL stack with two ultra-thick metal (UTM) layers was selected as one of the most critical learning vehicles to understand and quantify the effect of a high effective Cu thickness in combination with a reduced die thickness to match the package form factor requirements. With this vehicle, the “BEoL to bulk silicon thickness”-ratio can reach up to 10% or more, depending on die thickness. Based on a bi-material strip working hypothesis (bulk silicon + BEoL stack) an experiment design was devised with the aim of maximizing the assembly yield and minimizing the die warpage. Die thickness, Cu pillar solder height, BEoL metal density and assembly parameters have been selected as experiment design factors. The FC assembly was run in multiple experiments in a standard reflow process. The assembly yield was determined by inline x-ray inspection for non-wet failures and electrical test on packaged samples. The Shadow Moiré technique was used to collect substrate and die warpage hysteresis data in the temperature range in between RT and 260°C reflecting the behavior during the solder reflow process. The die warpage hysteresis was identified as a key factor for high assembly yields: the lower the hysteresis the lower the assembly yield loss. Additional cross sections were prepared to confirm the results of the X-Ray inspection and electrical tests. The critical fails occurred at the die corners showing non-wetting of the solder and matched the working hypothesis. The collected die warpage hysteresis data matched well with a prediction of the warpage hysteresis during the solder reflow using the rule of mixture for the BEoL CTE. With the collected results a forecast of the assembly yield loss in dependency of the different factors is possible. After solving the assembly challenges the packages were stressed in standard package reliability tests and passed the requirements. Additionally, assembly robustness tests were run (Multiple reflow, quick temperature cycle) and passed with margin.