Hardware Accelerator Design for Dynamic-Programming-Based Protein Sequence Alignment with Affine Gap Tracebacks

Dynamic programming methods are usually applied to solve the problem of protein sequence alignment. When designing hardware accelerators to speed up the alignment process, the memory usage of the traceback stage is always a concern. In this paper, we design a novel scheme for affine-gap traceback recording, which can reduce memory usage for traceback by 25%. In addition, with the observation that recording and retrieving of the traceback are executed in the opposite directions, we propose to utilize this last-in-first-out property on a shared memory so that recording and retrieving processes can be pipelined without requiring additional memory space. An ASIC design is implemented based on the proposed architecture using TSMC 40 nm technology, and the experiment shows that our hardware accelerator can speed up the pairwise alignment of protein sequences by 570×.