Non-Destructive 3D Characterization of Application Processor Panel Level Package Used in Galaxy Smartwatch

Modern wearable electronic devices have been available for nearly 35 years. However, in the past few years significant improvements have been made in the size, weight and usability of these products. While silicon scaling has contributed to achievement of these performance levels, newly developed IC packages are also key enabling technologies for these products. Wafer level package (WLP), panel level package (PLP) and package on package (POP) are technologies that are becoming increasingly popular for wearable and mobile products because they allow chips to be assembled into smaller packages, placed nearer to each other and joined with superior electrical interconnect systems. The Application Processor Module in the Galaxy Watch uses a novel PLP-POP design which meets both the performance requirements as well as the size requirements of Samsung's latest smartwatch. Previously, characterization of chips in IC packages with buried interconnects was done using traditional methodologies such as cross-section and optical microscopy. These techniques, however, can be slow and are prone to missing evidence that was not exposed by the cross-section cuts. New characterization methodologies such as X-ray inspection and measurement provide a richer, more complete assessment of these advanced designs. In this paper the Application Processor Module in the 2019 Galaxy Watch was characterized using a new type of non-destructive package inspection and measurement technology, known as X-ray Microscopy. Using this methodology, we were able to extract data and make conclusions on the results of the manufacturing processes, measure critical dimensions and assess key characteristics of the product, all done non-destructively with the Galaxy Watch PCB and Application Processor Module intact. Additional higher-resolution measurements could be made if the module was removed from the PCB and the shields.