A Comprehensive Analysis of Gate Drive Delay in CLLC Converters and Its Compensation Method

In this paper, the influences of gate drive signal delay caused by driver delay and power device parameters for CLLC converter are analyzed. This paper points out that the influences are equivalent to a phase shift and a change of duty cycle of PWM signal, and eventually can be demonstrated as four potential conditions. In some conditions, the operating process of the converter remains unchanged and the efficiency merely decreases slightly. However, in other conditions, the operating process changes a lot, where the circulating component of the secondary current is significant, and the ZCS feature of secondary power devices is lost. As a result, the efficiency decreases significantly. A compensation method is proposed and verified by experiments. By adopting proposed compensation method, the circulating current is suppressed, and the highest increase of efficiency is 8.66%.