Analysis of PCB return path configuration effect on Transient ESD Suppression

Since system level ESD testing is today applied to a wider range of products than ever before. Designing ESD robust systems can be very challenging, especially for systems which integrate advanced technology integrated circuit (IC) components. Solving ESD problems can lead to other complications on layout of chip and board level with verification. Since the ESD stress current makes its own path from injection spot to pins of IC under test or adjacent metal parts, such as trace or ground, we need to investigate those possible current paths forming a propagating chain on PCB of mounted component devices. A key finding of ESD design for sensitive IC mounted PCB is the analysis of the stress reaching IC / module/system level circuit so that best practice ESD protection and controls can be achieved. In this paper, we investigate the effect of different return paths on various ground plane configurations on board level ESD problem with the utilization of ESD generator model previously validated.