Implementation of a High-Resolution Symmetric PWM Based on Custom CMOS Delay Lines

An all-digital high-resolution symmetric pulse-width modulator based on a custom delay integrated circuit is presented. The topology uses two complementary trailing-edge PWM signals from an FPGA to set the coarse adjustment of the symmetric duty-cycles, and the fine adjustment is provided by digitally-controlled delay lines with adjustable time resolution, implemented in a custom integrated circuit. More than 20 dB of reduction in the total harmonic distortion plus noise (THD+N) was measured with the proposed approach for a 1 kHz signal.