Single Event Transient Compact Model for FDSOI MOSFETs Taking Bipolar Amplification and Circuit Level Arbitrary Generation Into Account

Single Event Transients (SET) are ionizing particles induced current pulses which are able to generate soft errors in CMOS circuits. In Silicon-on-Insulator (SOI) technologies, bipolar amplification phenomena is more significant due to presence of the Burried Oxide (BOX), which is detrimental to soft errors sensitivity. State of the art FDSOI SET models account for bipolar amplification through a dynamic pre-factor. This approach is mainly empirical and not compact. In this work, we propose a SET compact model for FDSOI MOSFETs including a physical modeling of bipolar amplification. Results are validated through TCAD simulations. A circuit level approach is proposed considering arbitrary generation within functional SRAM cell. This approach allows more realistic Single Event Upset (SEU) prediction and we show how circuit level generation can influence SEU prediction.