A VLSI Implementation of Double Precision Floating-Point Logarithmic Function

Logarithmic operations have a wide range of applications in the multimedia field, such as speech recognition, computer vision. Double-precision floating-point operations are widely used in scientific computing, so the development of high-performance floating-point logarithmic computing units has become one of the hot research topics. Based on the CORDIC (Coordinate Rotation Digital Computer) algorithm, this topic improves its operation cycle and demonstrates and implements the hardware design of the 64-bit floating-point logarithmic unit. It has the characteristics of a short cycle and high precision and meets the requirements of IEEE754. The hardware architecture is described in the Verilog language and simulated and integrated to derive its performance. With 100Hz clock and TSMC 65nm technology, the total area is about 0.2mm
²
, which needs only 16 clock cycles to calculate a double precision logarithmic function.