Optimization of Electrolytic Plating Processes for Challenging Fan-Out Panel Level Package Designs

The ever increasing demand for higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and device packaging. While on one hand design rules increase by complexity, manufacturing technologies are challenged to support both technical requirements and cost targets. Fan-out wafer level packaging is still considered a key enabler to support the technology roadmaps. This packaging platform had been introduced to the industry years ago and became a widely adopted packaging technology with various platforms now available in the market by key players of the industry. With the basic concept of creating an artificial substrate the traditional limitation of the available maximum wafer size becomes obsolete and the introduction of larger scale substrate in panel format seems straight forward, mainly driven by cost reduction purposes and system in package SiP applications which would benefit from the larger area. Batch processing of larger substrates promise to reduce manufacturing costs significantly by concept. One can think that panel based processing in areas like PVD, lithography and electroplating is a standard manufacturing technology, established in display and PCB applications and could be easily adopted. However the transfer of the traditional manufacturing methods require a high level of modifications in materials, processes and equipment solutions to become compatible with latest wafer level packaging applications and requirements. Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats, supported by tailored equipment and process solutions. PCBs and IC substrates is typically based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. Both areas currently merge and define a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. In this respect, the specific challenges in the area of electrolytic metal deposition is the creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper discusses latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design and pulse reverse rectification. An overview and comparison of typical plating systems will be presented. Finally, latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done either on panel or coupon level. The latest developments and findings of the discussed panel based plating technology will support the industry to transfer fan-out process technology from wafer to panel resulting in lower manufacturing costs.