Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity

With the development of internet and the rise of artificial intelligence industry, the high performance semiconductor integrated circuits have become a hot product in the semiconductor industry. The 2.5D IC package with ultra-high density I/O is the first structure applied on high performance computing (HPC) like GPU. Applied on GPU or HPC, there is an ASIC die and multiple HBM dice on silicon interposer. Between ASIC die and HBM die, there are lots of high speed signal lines between them and over hundreds of thousands of small vias. But the productivity of silicon interposer is always issue to realize the ultra-high density I/O products. To consider the productivity and performance, TSV-less structure like FOCoS (Fan-Out Chip on Substrate) is proposed by few years ago [1] [2] [3] [4] [5].There are Chip First FOCoS and Chip Last FOCoS for different process and application [6]. In this paper, a real case with an ASIC die and 2 HBM dice is designed in 2.5D IC and Chip Last FOCoS structures. In this real case, the interposer design and Fan-Out RDL is utilized SiP-id (System in Package intelligent design) design platform to accelerate the ultra-high density I/O routings. In addition, the electrical performance including signal integrity (SI) and power integrity (PI) are compared between 2.5D IC and Chip Last FOCoS. From the analysis results, the dynamic power noise between the two structures is showed in this paper and the electrical performance of HBM2 and 28Gbps SerDes I/Os are displayed as well.