Study of BEOL Failure Mode in Flip Chip Packages at High Temperature Conditions

As copper pillar bumps have been widely used in flip chip packages to meet the performance demand for denser IO bump and finer pitch, chip-package interaction (CPI) has been critical to achieving high yield rate and package reliability. With the increasing requirement for advanced technology nodes in high-performance devices, low-K (LK), extreme low-K (ELK) and ultralow-K (ULK) dielectric materials have been introduced in Back-End-Of-Line (BEOL) interconnects of silicon process. However, this poses a significant challenge for copper pillar bump interconnects in flip-chip packages since copper pillar is much stiffer than solder bump. During the cooling stage of chip attach reflow, a high stress could be induced in the fragile dielectric materials due to the thermal mismatch between the chip and substrate without any underfill protection right after chip attach. Intensive work has been studied to mitigate the CPI stress caused by the reflow process, such as package design optimization, cooling rate control, and assembly jig implementation, etc. Besides the BEOL dielectric delamination during chip attach, it was observed that the chip level LK/ELK failure could also occur even for assembled packages which already passed final test. It could happen during reliability tests or SMT process when packages go through a high temperature condition. This work presents a study of this failure mode and related mechanical mechanism. Flip chip using copper pillar bumps were tested in MSL 3 conditions to detect the failure mode. A multi-scale finite element model was developed to evaluate the CPI stress under different package conditions to understand the failure mechanism. First, a global model was built to include the bump array with individual bumps; then a detailed local bump model at fine scale with layered BEOL and copper pillar structure was built at the possible failed bump location to simulate stress on the dielectric layers. The simulation results have a good correlation with the test results to interpret the failure mode. The major factors impacting this failure mode include underfill material properties, polyimide opening (PIO), die thickness, UBM size, etc. are also studied. The simulation demonstrates the impact of package design associated with this failure mode.