Mechanism of Moldable Underfill (MUF) Process for RDL-1^st Fan-Out Panel Level Packaging (FOPLP)

In order to achieve higher productivity and lower cost, Fan-out Panel Level Packaging (FOPLP) is being developed recently to increase throughput significantly compared to FOWLP. Gen III panel with a size of 650mm×550mm is investigated in this study. However, large panel size makes the issues (such as voids, and warpage) more severe than FOWLP. In the present paper, RDL-1st approach is used. One of the major advantages of RDL-1 st process is to improve RDL process yield. This is due to chip-to-panel bonding is used before underfill/molding processes or modable underfill (MUF) process. MUF process has the advantage of simplified process steps. However, the challenge of moldability is increased with decreasing bump pitch and stand-off height. C-Scan or Thru-Scan test can obtain the void size, shape and location after molding. However, it is hard to analyze the mechanism of MUF process by only the testing results. Numerical simulation is a valuable way to track the transient information and make the whole process transparent. A large amount of fully populated chips with solder bumps are bonded onto the Gen-3 glass panel, which would demand high computational resources. More than 4000 bumps are located under each chip. Hence, it is difficult to use full model to construct the modeling. Instead, the simplified modeling is used to solve this issue. MUF process for liquid type EMC and sheet type EMC are simulated separately in the current study. The results show that packing pressure is one of the key factors for reducing voids for both types of EMC. Although lower molding speed is favorable in mold-1st process, it does not help in RDL-1 st process. Staggered bump layout design and large pitch help to reduce voids for sheet type EMC.