Hyper-Selective Co Metal ALD on Metals vs. SiO2 without Passivation

Integration of logic and memory into a single, monolithic 3D system-on-a-chip (SOC) allows for more efficient packing that can dramatically shorten (by 50 fold) computation times while using less power. For this 3D SOC vertical integration, high aspect ratio vias and interconnects need to be selectively deposited to induce the formation of larger grains and reduced resistivity. Here, low-temperature hyper-selective Co ALD was achieved utilizing an organometallic Co precursor and two different co-reactants that can allow for bottom-up via fill.