A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD)

A half-rate CDR architecture is presented which exploits an improved half-rate Linear Phase Detector (LPD) and a proposed half-rate Multi-Level Bang Bang PD (MLBBPD) incorporated in a Composite PD (CPD) to benefit the advantages of both the MLBBPD and LPD such as fast locking and good jitter performance, respectively. The proposed half-rate LPD in contrast with a conventional counterpart generates the error and reference signals with the equivalent pulse width, thus obviating to employ asymmetric charge pump, also relaxes the speed requirement of other related circuits. Finally, its systematic phase offset is zero. During lock acquisition, the MLBBPD controls the CDR loop due to fast lock time. At locked state, the LPD establishes the loop owing to better jitter operation. Switching between the MLBBPD and LPD is performed through a proposed Lock Detector (LD). At the locked state, if the phase difference between the data and the clock be greater than 45, the LD selects the MLBBPD to decrease it below 45, and again the LPD is selected. Simulations accomplished by Verilog-AMS model in HSPICE-RF simulator and the results confirm our statements.