A Novel 500-700V Ultra High-Voltage LDMOS with Low On-State Resistance by Multiple Local RESURF Enhancement Technology

In this work, a novel ultra high-voltage LDMOS device structure design is presented by multiple local RESURF enhancement technology to achieve breakdown voltage up to 500-700V as well as low on-state resistance. This innovative LDMOS structure is realized by using discontinuous shallow trench isolation (STI) in the P-top region which is located on the surface of the n-type drift region, while there is remaining n-type drift regions between the discontinuous STI above the P-top, thus the multiple n-p-n-p junction in the vertical direction is formed as the multiple local RESURF enhancement. The optimal charge balance and discontinuous STI geometrical design are investigated by 2D Sentaurus TCAD process and device simulators. Compared to the conventional RESURF structures, the electrical field of this presented device shows multiple equivalent peaks caused by local RESURF enhancement between every two adjacent disconnected STIs instead of a single strong peak, therefore the integrated electrical field with respect to depletion area, or the breakdown voltage, is greater. This allows the demonstration of better BVdss-Ron, sp trade-off as the power device figure of merit. Furthermore, this novel LDMOS structure can be manufactured by conventional active-area (AA) process without any additional fabrication cost.