Area-Power-Delay Trade-Off in Ternary FPRM Circuits Based on MOTLBO Algorithm

With the development of multi-valued logic circuits, requirements of their EDA design are growing, which requires the support of high-performance algorithms. A scheme based on multi-objective teaching and learning optimization algorithm (MOTLBO) is proposed to find the optimal polarity of area, power and delay for ternary fixed polarity Reed-Muller (FPRM) logistic circuits. Firstly, the estimation model of area, power and delay for ternary FPRM circuit is established through analyzing the logic expression of ternary FPRM. Then, the optimal polarity of area, power and delay is searched by combining MOTLBO algorithm with ternary FPRM circuit polarity conversion technology. Finally, experiments on PLA format MCNC Benchmarks show that the presented method achieves competitive or better performance than existing method.