A General DTC Nonlinearity Calculation Method for the ADPLL Spur Analysis

In this paper, we propose a general DTC (Digital-to-Time Converter) nonlinearity calculation method, and use it to predict the spur level of ADPLL (All Digital Phase-Locked Loops), no matter which form the non-linearity of DTC is. Previous methods can only calculate the DTC non-linearity with sinusoidal form, while are unable to treat the non-linearity in non-sinusoidal form. Using the proposed method, the DTC non-linearity of different non-sinusoidal forms are calculated and compared to the circuit simulation results, and good agreement is found.