A Method for Measuring Resistance of Metal Interconnection Inside Chip

In the manufacturing of integrated circuit, some anomaly occurs to back-end metal interconnection. When the anomaly cannot be monitored by WAT or PCM (such as random defects or defects only appear at special patterns), it is necessary to measure the resistance of metal lines or vias in certain positions in the chip. The conventional method is to prepare samples with FIB: perform partial etching and connection on the chip, then measure the resistance with probe station. But when the metal structure is special or the CD is very small, sample preparation will be extremely difficult. For the above cases, this paper introduces a new measurement method: remove the silicon substrate of chip by some physical and chemical methods first, then probe on the metal or via using Nano probe to measure the resistance. This method dramatically increases the success rate of sample preparation. In addition, this method can also be used to measure some devices made by back-end metal like MIM, etc.